In this article, will solicit the poster session for RISC-V Day Tokyo 2024 and the deadline for poster session submission was extended to July 20, 2024 (Saturday).
press release
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RISC-V Day Tokyo Summer 2024 ポスターセッションの提出期限を延長
東京, 2024年7月4日 - RISC-V Day Tokyo Winter 2024のオーガナイザーは、関連WEBサイトで公表されていたポスターセッションの提出期限を2024年7月20日(土)まで延長することを発表します。当初の締め切りは2025年6月30日でしたが、参加者からのご要望に応える形でこの変更を行います。
この延長により、更なる革新的なアイデアや研究がRISC-Vコミュニティに紹介される機会が増えることを期待しています。RISC-V Day Tokyoは、リアルタイムシステム、ネットワークプログラミング、情報セキュリティなど、多岐にわたるトピックに焦点を当てています。
RISC-V Day Tokyo Summer 2024 poster session submission deadline extended
Tokyo, July 4, 2024 - The organizers of RISC-V Day Tokyo Summer 2024 are pleased to announce that the poster session submission deadline has been extended to Saturday, July 20, 2024. The original deadline was June 30, 2024, but this change was made in response to requests from participants.
We hope that this extension will provide more opportunities for further innovative ideas and research to be introduced to the RISC-V community. RISC-V Day Tokyo focuses on a wide variety of topics including real-time systems, network programming, and information security.
RISC-V Day Tokyo Summer 2024 offers a deep dive into the latest technology trends, industry challenges, and the future of RISC-V architecture. This event is a valuable networking opportunity for industry professionals, researchers, and developers.
We look forward to your active participation and sharing your innovative ideas.
Contact information: RISC-V Day Tokyo Winter 2024 Management Office RISC-V Association General Incorporated Association Director Representative shumpei<dot>kawasaki<at>swhwc.com shumpei<dot>kawasaki<at>riscv.or.jp 03-5565-05556 070-2803-8231
7/4/2024 In this RISC-V Day, we will hold a poster session to share the latest technology and research. We are looking forward to your participation and interaction with many participants. To increase researcher’s exposure, develop careers, provide feedback and learning, enhance communication skills, and discover their own characteristics, RISC-V Day will add the following activities to the regular poster session for those who wish to.
How System Works 1. For researchers who hold a poster session, the conference participation fee will be free. 2. Participants will be given the opportunity to give a podium presentation in addition to explaining the poster, and the presentation will be video recorded. 3. This recorded video will be posted on the web, along with a PDF for the presentation, reaching a wider audience. 4. On the web, the participant’s presentation will be posted, and we will make it a high page rank in search. 5. The presentation does not have to be new content. Introductions to existing research and projects are alsowelcome. It is an opportunity to introduce your interests and experiments. 6. For those who wish, we will prepare a desk and power supply. Participants can do demos. The following are the same as a normal poster session but let me explain the details. 7. Poster session participants are provided with individual panels (90cm x 180cm or 210cm), and if necessary the organizer will prepare an A0 size poster by themselves. If desired, a side table will be set up next to the panel, and power and WiFi are planned to be provided. 8. The poster session is considered part of the presentation, and participants explain to visitors at their own panels. 9. We will arrange a coordination (including hosting) of the podium presentation. 10. Video recording, web creation, etc. will be prepared by the organizer.
Call for Themes: At RISC-V Day, we are calling for poster sessions on the following fields. These themes show new approaches to meet expanding computational needs and sustainability challenges. 1 RISC-V technology: Instruction sets, microarchitecture, integrated circuits, IP, chips, systems, software, and the implementation of RISC-V extensions/customizations. 2 Open-Source Hardware Revolution: Open silicon starting with RISC-V Green Computing: Techniques for reducing energy consumption in computing environments, including RISC-V based solutions. 3 Hardware and Software Co-design: Examples and case studies showing the impact of RISC-V and open-source hardware or software development, and vice versa. 4 AI and Machine Learning: Role of RISC-V in accelerating AI/ML workloads, customizing hardware for AI/ML, etc. 5 Real World Applications: Industry or research projects that have used RISC-V in product development, research outcomes, etc. 6 Security technologies for open architecture 7 AIoT, IoT RISC-V Architecture 8 Quantum Computing 9 Secret Computing - Privacy-enhancing data analysis technology represented by Homomorphic Encryption, which computes with encrypted data. 10 Emerging Computing Topic: Topics like neuromorphic computing, bio-inspired computing, and new forms of non- volatile memory technologies. 11 High-Performance Computing (HPC): The use of RISC-V in HPC applications, challenges, and innovations in creating competitive RISC-V based HPC systems. 12 Edge Computing: The role of RISC-V in the growth of edge computing, including applications in smart cities, autonomous vehicles, and IoT. 13 5G/6G Technologies: How RISC-V can be incorporated into the next generation of telecommunications infrastructure and the role it plays in network devices. 14 Blockchain and Distributed Ledger Technologies: Use cases of RISC-V in blockchain hardware, smart contracts, and how it can provide secure and efficient computation in decentralized systems. 15 Quantum-resistant Cryptography: With the advent of quantum computing, exploring how RISC-V can be used to develop quantum-resistant cryptographic solutions. 16 Cross-platform Development Tools: Tools that support RISC-V development across different platforms, easing the development process and fostering wider adoption. 17 Interoperability with Other Architectures: How RISC-V interfaces with other architectures, emulation, and virtualization technologies to create hybrid systems. 18 Sustainable and Eco-friendly Computing: Beyond just green computing, a focus on how RISC-V hardware can be designed with sustainability in mind, including recyclable materials, energy harvesting, and lifecycle analysis. 19 Digital Signal Processing (DSP): Applications of RISC-V in DSP for audio, video, and communications technologies. 20 Space Technology: The use of RISC-V in space applications, which could include satellites, rovers, and other space exploration hardware. 21 Educational Initiatives: How RISC-V is being used for educational purposes, in teaching computer architecture, hardware design, and fostering a new generation of engineers. 22 Medical and Biotech Applications: Implementation of RISC-V in medical devices, biotechnology, and personalized medicine, including wearable technologies. 23 Automotive and Transportation Systems: The role of RISC-V in the future of transportation, including self-driving cars, electric vehicle systems, and more. 24 Formal Verification for RISC-V: Approaches to ensuring the correctness and security of RISC-V processors through formal methods. 25 Cultural and Societal Impacts of Technology: Discussing the broader impacts of open-source hardware and RISC-V on society, accessibility, and digital divide issues.
In addition to the above, we are soliciting poster sessions on a wide range of RISC-V related fields. We will review new ideas, research results, business applications, etc., with an open mind, so please feel free to apply.
Schedule: ● Abstract registration deadline: July 20, 2024 ● Submission deadline: July 30, 2024 If the proposal arrives early, we will inform you of the acceptance/rejection result before December 28. Submission Guidelines: Submission site: https://easychair.org/cfp/RVDaysTokyo2024Winter ● The poster should be of A0 size, portrait orientation. ● The title, authors and their affiliations should be clearly visible at the top of the poster. ● The poster should be easy to read from 1.5 meters. ● The authors are required to include an abstract (up to 250 words) along with their submission.
Assessment Criteria: The posters will be judged based on the following criteria: ● Originality and novelty of the research/idea. ● Quality and clarity of the research methodology. ● Relevance to the themes of the conference. ● Quality of the poster design and presentation.
Award: The best poster will be awarded at the closing ceremony of the conference, based on the assessment of the judges. We look forward to your active participation in RISC-V Day! Let’s contribute to the evolution of computing technology and sustainability together with RISC-V. (Note: Please ensure to adhere to COVID-19 safety guidelines as recommended by the health authorities during the conference.)
1. Event name: RISC-V Day Tokyo 2024 Winter RISC-V Day Tokyo 2024 Winter
2. Date, time and method: January 16, 2024 (Tuesday) 9:00 - 17:00 (Japan Time) The University of Tokyo, Hongo Campus, "Ito International Academic Research Center"Ito International Thank You Hall, foyer, multipurpose space, Gallery 1, Gallery 2, etc. use
4. Purpose and content: The RISC-V Association will sponsor "RISC-V Day Tokyo 2024 Winter"on LAugust 1, 2024. Risk Five Day is a venue for presentations by Risk Five researchers, engineers, and suppliers. We will bring together outstanding technology presentations and engineers related to RISC-V, including areas such as AI domain dedicated processors for data centers, AIoT systems, security, open silicon, and quantum computers, to improve technology awareness and help companies We provide opportunities for realizing academic collaboration, technical exchange, information gathering, etc.
6. Sponsorship (planned) RISC-V International (Switzerland), RISC-V Association (Japan), RISC-V Working Group (Japan), Embedded Systems Technology Association, NEDO New Energy and Industrial Technology Comprehensive Development Organization
7. Support from the RISC-V Association: Support for holding conferences by association members
8. Management of RISC-V Days: SH Consulting Co., Ltd. 7-18-13-502 Ginza, Chuo-ku, Tokyo 104-0061 Haruyuki Tago (Secretariat) Phone: 03-5565-0556, E-mail: haruyuki<dot>tago<at>swhwc<dot>com
9. RISC-V Alliance Japan Trade name: RISC-V Alliance Japan Representative Director Shumpei Kawasaki (Kawasaki Shunpei) Office address: 7-18-13-502 Ginza, Chuo-ku, Tokyo 104-0061 TEL 03-5565-0556 Industry Other: Corporations with fewer than 10 employees Official blog http://riscv.or.jp
10. RISC-V Association supporting member; Embedded Systems Technology Association (Japan)